1. Field of the Invention
This invention generally relates to semiconductor memory devices, and, in particular, to controlling a data strobe signal for accessing memory in a memory device.
2. Description of the Related Art
Modern integrated circuit devices are comprised of millions of semiconductor devices, e.g., transistors, formed above a semiconductor substrate, such as silicon. These devices are very densely packed, i.e., there is little space between them. Similarly, densely packed electrically conducting lines may also be formed in the semiconductor substrate. By forming selected electrical connections between selected semiconductor devices and selected conducting lines, circuits capable of performing complex functions may be created. For example, bits of data may be stored by providing electrical current to a plurality of bit lines and an orthogonal plurality of wordlines that may be electrically coupled to one or more capacitors in a semiconductor memory.
The semiconductor memory may be a dynamic random access memory, a flash memory, and the like. The semiconductor memory typically comprises an array of memory cells, address decoding circuitry for selecting one, or a group, of the memory cells for reading or writing data, sensing circuitry for detecting the digital state of the selected memory cell or memory cells, and input/output lines to receive the sensed data and convey that information for eventual output from the semiconductor memory. In many cases, the array of memory cells will be sub-divided into several sub-arrays, or subsets, of the complete collection of memory cells. For example, a semiconductor memory having 16 megabits (224 bits) of storage capacity, may be divided into 64 sub-arrays, each having 256K (218) memory cells.
Flash memory (sometimes called “flash RAM”) is a type of non-volatile memory that can be erased and reprogrammed in units of memory called blocks. Flash memory is a variation of electrically erasable programmable read-only memory (EEPROM) that, unlike flash memory, is erased and rewritten at the byte level, which is slower than flash memory updating. Flash memory is commonly used to hold control code such as the basic input/output system (BIOS) in a personal computer. When BIOS needs to be changed (rewritten), the flash memory can be written in block (rather than byte) sizes, making it faster to update. Applications employing flash memory include digital cellular phones, digital cameras, LAN switches, computers, digital set-up boxes, embedded controllers, and other devices. These applications generally call for extensive memory access.
Accessing memory requires a circuit to capture the address and data at precise timing in relation to clock signals that drive a circuit. Errors occurring during the capturing of addresses and data may cause errors in accessing the data stored in memory. Many times external factors, such as temperature drifts, voltage-level drifts, and the like, can affect a window of a time period when data and/or addresses may be captured by a circuit. In order to acquire, access, or capture data and/or addresses during transfer of memory data from one device to another, precise clocking of the data and addresses and their timing is desirable.
Many of today's memory devices, such as double data rate RAM devices (DDR RAM), require intricate timing schemes for proper operation. Often external clocks may be used to clock the operations of the memory device, which may be prompted by an external device such as a processor. The memory devices may contain an inherent latency in the operation and reaction to commands and clock signals from external sources. For example, there may be an inherent latency between the time that an external device, such as a processor, makes a request or sends a command for a particular memory operation to the memory device, and the time that the memory device actually reacts to such instructions.
Typically, digital systems, such as memory systems, may comprise a delay lock loop that may be used to align the edges of a plurality of digital signals. For example, a delay lock loop circuit may be used to align the rising edge and/or the falling edge of a clock signal based upon an external or system clock (which may be used as a reference clock signal), to produce a synchronized clock signal. Many times, digital signals from multiple sources access one or more memory spaces in a memory unit. It is desirable that these digital signals be synchronized for proper access of memory. Typical delay lock loops comprise a phase detect unit that detects the phase differences between a plurality of signals. The output of the phase detect unit is then used to affect the operation of a filter that adjusts the delay of an output of the delay lock loop.
In timing sensitive applications such as DDR RAM applications, the latency time and the proper reaction to external commands becomes important in assuring proper memory operations. For example, a read signal sent to the DDR RAM or a memory device, may prompt a reaction by the memory device to provide data on a data bus in reaction to the read request. However, external factors, such as changes in operating voltage and changes in temperature during the operation of the device, may cause a change in the operation timing of the device. Changes in the operation timing may cause a device to provide data at a time when the data bus access may not be valid, causing operation errors.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.